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1. general description the npic6c596 is an 8-bit serial-in/serial or parallel-out shift register with a storage register and open-drain outputs. both the shift and storage re gister have separate clocks. the device features a serial input (ds) and a serial output (q7s) to enable cascading and an asynchronous reset mr input. a low on mr resets both the shift register and storage register. data is shifted on the low-to-high transitions of the shcp input. the data in the shift register is transferred to the storag e register on a low-to-high transition of the stcp input. if both clocks ar e connected toge ther, the shift register is always one clock pulse ahead of the storage register. to provide additional hold time in cascaded applications, the serial output qs7 is clocke d out on the falling edge of shcp. data in the storage register drives the gate of the ou tput extended-drain nmos (ednmos) transistor whenever the output enable input (oe ) is low. a high on oe causes the outputs to assume a high-impedance off-state. operation of the oe input does not affect the state of the registers. the open-drain outputs are 33 v/100 ma co ntinuous current extended-drain nmos transistors designed for use in systems that require moderate load power such as leds. integrated voltage clamps in the outputs provide protection against inductive transients making the device suitable for power driver applications such as relays, solenoids and other low-current or medium-voltage loads. 2. features and benefits ? specified from ? 40 ? cto+125 ? c ? low r dson ? eight power ednmos transistor outputs of 100 ma continuous current ? 250 ma current limit capability ? output clamping voltage 33 v ? 30 mj avalanche energy capability ? enhanced cascading for multiple stages ? all registers cleared with single input ? low power consumption ? esd protection: ? hbm jds-001 class 2 exceeds 2500 v ? cdm jesd22-c101e exceeds 1000 v npic6c596 power logic 8-bit shift re gister; open-drain outputs rev. 2 ? 4 july 2013 product data sheet
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 2 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs 3. applications ? led sign ? graphic status panel ? fault status indicator 4. ordering information 5. functional diagram table 1. ordering information type number package temperature range name description version NPIC6C596D ? 40 ? c to +125 ? c so16 plastic small outline package; 16 leads; body width 3.9 mm sot109-1 npic6c596pw ? 40 ? c to +125 ? c tssop16 plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 npic6c596bq ? 40 ? c to +125 ? c dhvqfn16 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 ? 3.5 ? 0.85 mm sot763-1 fig 1. logic symbol fig 2. functional diagram q0 ds shcp mr stcp q1 3 15 10 2 4 5 6 11 12 13 14 9 78 q2 q3 q4 q5 q6 q7 q7s oe aaa-002547 3 q0 4 q1 5 q2 6 q3 open-drain outputs 8-bit storage register 8-stage shift register 11 q4 12 q5 13 q6 14 q7 oe stcp mr shcp q7s ds 2 15 9 7 10 8 aaa-002548
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 3 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs fig 3. schematic of all inputs fig 4. schematic of open-drain outputs (qn) aaa-002550 gnd v cc aaa-002551 gnd qn 33 v fig 5. logic diagram aaa-002552 gnd q ddq q q7s q7 stage 7s stage 7 stage 1 to 6 stage 0 cp dq r rr cp ff7 dq ds shcp mr stcp oe cp r ff0 latch ff7 d cp dq r cp latch q6q5q4q3q2q1q0 gnd
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 4 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs fig 6. timing diagram aaa-002553 7654321 5 v gnd shcp oe ds 5 v gnd 5 v gnd 5 v gnd 5 v gnd v oh v ol 0 stcp mr q1
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 5 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs 6. pinning information 6.1 pinning 6.2 pin description (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 7. pin configuration so16 and tssop16 fig 8. pin configuration dhvqfn16 npic6c596 v cc gnd ds shcp q0 q7 q1 q6 q2 q5 q3 q4 mr stcp oe q7s aaa-003484 1 2 3 4 5 6 7 8 10 9 12 11 14 13 16 15 aaa-003485 npic6c596 mr stcp q3 q4 q2 gnd (1) q5 q1 q6 q0 q7 ds shcp oe q7s v cc gnd transparent top view 7 10 6 11 5 12 4 13 3 14 2 15 8 9 1 16 terminal 1 index area table 2. pin description symbol pin description v cc 1 supply voltage ds 2 serial data input q0, q1, q2, q3, q4, q5, q6, q7 3, 4, 5, 6, 11, 12, 13, 14 parallel data output (open-drain) mr 7 master reset (active low) oe 8 output enable input (active low) q7s 9 serial data output stcp 10 storage register clock input shcp 15 shift register clock input gnd 16 ground (0 v)
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 6 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs 7. limiting values [1] each power ednmos source is internally connected to gnd. [2] pulse duration ? 100 ? s and duty cycle ? 2 %. [3] v ds = 15 v; starting junction temperature (t j ) = 25 ? c; l = 1.5 h; avalanche current (i al ) = 200 ma. [4] for so16 packages: above 25 ? c the value of p tot derates linearly with 6.4 mw/ ? c. for tssop16 packages: above 25 ? c the value of p tot derates linearly with 5.8 mw/ ? c. for dhvqfn16 packages: above 25 ? c the value of p tot derates linearly with 14.6 mw/ ? c. table 3. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +7.0 v v i input voltage ? 0.3 +7.0 v v ds drain-source voltage power ednmos drain-source voltage [1] -+33 v i d(sd) source-drain diode current continuous - 250 ma pulsed [2] -500 ma i d drain current t amb = 25 ? c continuous; each output; all outputs on -100 ma pulsed; each output; all outputs on [2] -250 ma i dm peak drain current single output; t amb = 25 ?c [2] -250 ma e as avalanche energy single pulse; see figure 9 [3] -30 mj i al avalanche current see figure 9 [3] -200 ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = 25 ? c [4] so16 - 800 mw tssop16 - 725 mw dhvqfn16 - 1825 mw t amb = 125 ?c [4] so16 - 160 mw tssop16 - 145 mw dhvqfn16 - 365 mw
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 7 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs 7.1 test circuit and waveform 8. recommended operating conditions [1] pulse duration ? 100 ? s and duty cycle ? 2 %. [2] technique should limit t j ? t amb to 10 ? c maximum. 9. static characteristics (1) the word generator has the following characteristics: t r ,t f ? 10 ns; z o = 50 ? . (2) the input pulse duration (t w ) is increased until peak current i al = 200 ma. energy test level is defined as: e as =i al ? v (br)dss ? t al /2 = 30 mj. fig 9. test circuit and waveform for measuring single-pulse avalanche energy aaa-002556 word generator (1) dut 7 1 5 v 15 v 5 v min 0 v l al = 200 ma v (br)dss = 33 v i d v ds 30 1.5 mh 16 gnd oe stcp ds shcp mr v cc v ds l d qn 15 2 10 3-6, 11-14 8 t w (2) t al table 4. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage 4.5 - 5.5 v v i input voltage 0 - 5.5 v i d drain current pulsed drain output current; v cc =5v; t amb = 25 ?c; all outputs on [1] [2] --250ma t amb ambient temperature ? 40 - +125 ?c table 5. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions v cc = 5.0 v; t amb = 25 ?c unit min typ max v ih high-level input voltage v cc = 4.5 v to 5.5 v 0.85v cc --v v il low-level input voltage v cc = 4.5 v to 5.5 v - - 0.15v cc v v oh high-level output voltage serial data output q7s; v i =v ih or v il i o = ? 20 ? a; v cc = 4.5 v 4.4 4.49 - v i o = ? 4ma; v cc = 4.5 v 4.0 4.2 - v
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 8 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs [1] output currents below 250 ma current limit. [2] technique should limit t j ? t amb to 10 ? c maximum. [3] these parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. [4] nominal output current is defined for a consistent comparis on between devices from different sources. it is the current that produces a voltage drop of 0.5 v at t amb = 85 ? c. v ol low-level output voltage serial data output q7s; v i =v ih or v il i o =20 ? a; v cc = 4.5 v - 0.005 0.1 v i o =4ma; v cc = 4.5 v - 0.3 0.5 v i ih high-level input current v cc = 5.5 v; v i =v cc --1 ? a i il low-level input current v cc = 5.5 v; v i =0 v ? 1-- ? a v (br)dss drain-source breakdown voltage i d = 1 ma 33 37 - v v sd source-drain voltage diode forward voltage; i f = 100 ma - 0.85 1.2 v i cc supply current logic supply current; v cc = 5.5 v; v i =v cc or gnd all outputs off - 0.004 200 ? a all outputs on [1] - 0.006 500 ? a all outputs off; shcp = 5 mhz; c l =30pf; see figure 14 and figure 16 -0.755ma i o(nom) nominal output current v ds = 0.5 v; t amb =85 ?c; i out = i d [2] [3] [4] - 140 - ma i dsx drain cut-off current v cc = 5.5 v; v ds = 30 v - 0.002 0.2 ? a v cc = 5.5 v; v ds = 30 v; t amb = 125 ?c - 0.15 0.3 ? a r dson drain-source on-state resistance see figure 17 and figure 18 [2] [3] v cc = 4.5 v; i d = 50 ma - 3.0 9 ? v cc = 4.5 v; i d = 50 ma; t amb = 125 ?c5 . 4 1 2 ? v cc = 4.5 v; i d = 100 ma - 3.1 10 ? table 5. static characteristics ?continued at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions v cc = 5.0 v; t amb = 25 ?c unit min typ max
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 9 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs 10. dynamic characteristics [1] t pd is the same as t plh and t phl . [2] this is the maximum serial clock frequency assuming cascaded operation where seri al data is passed from one stage to a secon d stage. the clock period allows for shcp q7s propagation delay and setup time plus some timing margin. [3] technique should limit t j ? t amb to 10 ? c maximum. [4] these parameters are measured with voltage-sensing contacts separate from the current-carrying contacts. 10.1 test circuits and waveforms table 6. dynamic characteristics voltages are referenced to gnd (ground = 0 v); for test circuit see figure 14 . symbol parameter conditions v cc = 5.0 v; t amb = 25 ?c unit min typ max t plh low to high propagation delay oe to qn; i d = 75 ma; see figure 10 and figure 19 -97-ns t phl high to low propagation delay oe to qn; i d = 75 ma; see figure 10 and figure 19 -9-ns t r rise time oe to qn; i d = 75 ma; see figure 10 and figure 19 -60-ns t f fall time oe to qn; i d = 75 ma; see figure 10 and figure 19 -18-ns t pd propagation delay shcp to q7s; i d = 75 ma; see figure 11 [1] -5-ns f max maximum frequency shcp; i d = 75 ma; see figure 11 [2] --10mhz t rr reverse recovery time i f = 100 ma; di/dt = 10 a/ ? s; see figure 13 [3] [4] - 120 - ns t a reverse recovery current rise time i f = 100 ma; di/dt = 10 a/ ? s; see figure 13 [3] [4] - 100 - ns t su set-up time ds to shcp; see figure 12 15 - - ns t h hold time ds to shcp; see figure 12 15 - - ns t w pulse width 40 - - ns measurement points are given in table 7 . v ol is the typical output voltage level that occurs with the output load. fig 10. the output enable (oe ) input to data output (qn) propagation delays and (qn) output rise and fall times gnd 24 v t plh t r v m v i v ol v x v x v y t phl t f v y qn output low-to-off off-to-low oe input aaa-002557
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 10 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs measurement points are given in table 7 . v ol and v oh are the typical output voltage levels that occur with the output load. fig 11. the shift clock (shcp) to serial data output (q 7s) propagation delays with the minimum shift clock pulse width and maximum shift clock frequency aaa-002558 shcp input q7s output v i gnd v oh v ol 1/f max t phl v m v m t plh t w table 7. measurement points supply voltage input output v cc v m v m v x v y 5 v 0.5v cc 0.5v ds 0.1v ds 0.9v ds measurement points are given in table 8 . the shaded areas indicate when the input is per mitted to change for predictable output performance. v ol and v oh are the typical output voltage levels that occur with the output load. fig 12. the data set-up and hold ti mes for the serial data input (ds) aaa-002559 shcp input ds input q7s output v i gnd v i gnd v oh v ol v m v m v m t su t su t h t h table 8. measurement points supply voltage input output v cc v m v m 5 v 0.5v cc 0.5v cc
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 11 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs (1) the open-drain qn terminal under test is connected to test point k. all other terminals ar e connected together and connected to test point a. (2) the v i amplitude and r g are adjusted for di/dt = 10 a/ ? s. a v i double-pulse train is used to set i f = 0.1 a, where t 1 = 10 ? s, t 2 = 7 ? s and t 3 = 3 ? s. fig 13. test circuit and waveform for measuring reverse recovery current aaa-002560 i f dut qn 15 v driver r g g 50 2500 f 250 v 0.85 mh k (1) a (1) t 1 t 2 t 3 v i (2) 0.1 a di/dt = 10 a/s i f t a t rr 0 25 % of l rm i rm
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 12 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs (1) the word generator has the following characteristics: t r , t f ? 10 ns; t w = 300 ns; pulsed repetition rate (prr) = 5 khz; z o = 50 ? . (2) c l includes probe and jig capacitance. test data is given in table 9 . definitions for test circuit: v ds = external voltage for power ednmos drain-source voltage. r l = load resistance. c l = load capacitance including jig and probe capacitance. fig 14. test circuit for measuring switching times 7 15 2 10 16 gnd 1 t w t w 90 % v m 10 % 0 v positive pulse negative pulse v i 0 v v i v m v m v m 90 % t f t r t r t f 10 % word generator (1) 8 v cc 5 v qn 3, 4, 5, 6 11, 12,13, 14 aaa-002561 v ds = 15 v r l c l (2) mr ds oe shcp stcp table 9. test data supply voltage input load v i t r , t f v m c l r l 5v 5v ? 10 ns 50 % 30 pf 200 ?
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 13 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs t amb = 25 ? c. t amb = ?40 ? c to +125 ? c; v cc = 5 v. fig 15. avalanche current (peak) versus time duration of avalanche fig 16. supply current versus frequency t al (ms) 10 -1 10 1 aaa-002562 10 -1 1 i al (a) 10 -2 aaa-002563 2 4 6 l cc (ma) 0 f i (mhz) 10 -1 10 2 10 1 v i = v cc or gnd and v o = gnd or v cc . (1) t amb = 125 ?c (2) t amb = 85 ? c (3) t amb = 25 ? c (4) t amb = ?40 ? c v i = v cc or gnd and v o = open circuit. (1) t amb = 125 ?c (2) t amb = 85 ? c (3) t amb = 25 ? c (4) t amb = ?40 ? c fig 17. drain-source on-state resistance versus drain current fig 18. static drain-source on-state resistance versus supply voltage l d (ma) 50 300 250 150 200 100 aaa-002564 2 3 1 4 5 r dson () 0 (4) (3) (1) (2) v cc (v) 48 7 56 aaa-002565 2 3 1 4 5 r dson () 0 (1) (2) (3) (4)
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 14 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs technique limit t j ? t c to 10 ? c maximum. (1) t plh . (2) t r . (3) t f . (4) t phl . fig 19. switching time versus case temperature aaa-002546 t amb (c) -50 0 50 100 125 75 25 -25 140 switching time (ns) 0 20 40 60 80 100 120 (1) (2) (3) (4)
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 15 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs 11. package outline fig 20. package outline sot109-1 (so16) x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 8 9 1 16 y pin 1 index unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 10.0 9.8 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot109-1 99-12-27 03-02-19 076e07 ms-012 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.39 0.38 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.020 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 0 2.5 5 mm scale so16: plastic small outline package; 16 leads; body width 3.9 mm sot109-1
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 16 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs fig 21. package outline sot403-1 (tssop16) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.40 0.06 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot403-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 18 16 9 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop16: plastic thin shrink small outline package; 16 leads; body width 4.4 mm sot403-1 a max. 1.1 pin 1 index
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 17 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs fig 22. package outline sot763-1 (dhvqfn16) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.6 3.4 d h 2.15 1.85 y 1 2.6 2.4 1.15 0.85 e 1 2.5 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot763-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot763-1 dhvqfn16: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 16 terminals; body 2.5 x 3.5 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 27 15 10 9 8 1 16 x d e c b a terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1) 02-10-17 03-01-27
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 18 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs 12. abbreviations 13. revision history table 10. abbreviations acronym description cdm charged device model cmos complementary metal oxide semiconductor dut device under test ednmos extended drain negative metal oxide semiconductor esd electrostatic discharge hbm human body model ttl transistor-transistor logic table 11. revision history document id release date data sheet status change notice supersedes npic6c596 v.2 20130704 product data sheet - npic6c596 v.1 modifications: ? figure 5 corrected (errata). npic6c596 v.1 20120821 product data sheet - -
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 19 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs 14. legal information 14.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 14.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any lic ense under any copyrights, patents or other industrial or intellectual property rights. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
npic6c596 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 4 july 2013 20 of 21 nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. non-automotive qualified products ? unless this data sheet expressly states that this specific nxp semicon ductors product is automotive qualified, the product is not suitable for automotive use. it is neither qualified nor tested in accordance with automotive testing or application requirements. nxp semiconductors accepts no liabili ty for inclusion and/or use of non-automotive qualified products in automotive equipment or applications. in the event that customer uses t he product for design-in and use in automotive applications to automotive specifications and standards, customer (a) shall use the product without nxp semiconductors? warranty of the product for such automotive applicat ions, use and specifications, and (b) whenever customer uses the product for automotive applications beyond nxp semiconductors? specifications such use shall be solely at customer?s own risk, and (c) customer fully indemnifies nxp semiconductors for any liability, damages or failed product claims resulting from customer design and use of the product for automotive app lications beyond nxp semiconductors? standard warranty and nxp semiconduct ors? product specifications. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 14.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 15. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors npic6c596 power logic 8-bit shift register; open-drain outputs ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 4 july 2013 document identifier: npic6c596 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 16. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 applications . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2 4 ordering information . . . . . . . . . . . . . . . . . . . . . 2 5 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 6 pinning information . . . . . . . . . . . . . . . . . . . . . . 5 6.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 6.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 5 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 6 7.1 test circuit and waveform . . . . . . . . . . . . . . . . . 7 8 recommended operating conditions. . . . . . . . 7 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 7 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 9 10.1 test circuits and waveforms . . . . . . . . . . . . . . . 9 11 package outline . . . . . . . . . . . . . . . . . . . . . . . . 15 12 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 18 13 revision history . . . . . . . . . . . . . . . . . . . . . . . . 18 14 legal information. . . . . . . . . . . . . . . . . . . . . . . 19 14.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 19 14.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 14.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 20 15 contact information. . . . . . . . . . . . . . . . . . . . . 20 16 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21

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